1. Field of the Invention
This invention relates to the field of digital systems employing non-volatile (or flash) memory and particularly multi level cell (MLC) flash.
2. Description of the Prior Art
Solid state memory or non-volatile memory, in the form of flash, is readily employed in numerous applications requiring saving and retrieving digital information. Some use thereof includes memory sticks, disk drives, personal digital assistants (PDAs) and other digital mobile devices.
NAND flash memory is a type of flash memory constructed from electrically-erasable programmable read-only memory (EEPROM) cells, which are an array of floating gate transistors. NAND refers to the type of gate used in the flash memory. NAND flash memory uses tunnel injection for write and tunnel release during erase operations. NAND flash, which is a type of non-volatile memory, is ideal for storage of digital information in portable devices.
However, NAND flash memory does have limitations. Namely, in flash, digital information or data is stored as binary information, i.e. ‘1’ or ‘0’. One limitation posed by NAND flash memory is that during storage of data, which occurs during writing to or programming of the flash memory, data that is ‘1’s can only be stored in the flash memory. Data that is ‘0’s cannot be store until erase occurs of the previously-stored data. In fact, when writing from a state of ‘0’ to a state of ‘1’, the flash memory needs to be erased a “block” at a time, which is undesirable as it adversely affects performance by way of efficiency. The reason for the requirement for erasing a “block” at a time is that while the smallest unit for a read or program operation to NAND flash memory is a byte (eight bits) or a word, the smallest unit for erase is a block. A bit of information or data is represented by a ‘1’ or ‘0’. A block refers to one or more pages of information made of bytes or words, and that which is erasable as a unit. An exemplary page size is 2 kilo (K) bytes of which may be reserved for data and 64 bytes of which are reserved for spare. The structure of a page can be either 4*512+64 bytes or 4*(512+16) bytes, the 512 bytes being used for data and the 16 bytes for address flag, error correction code (ECC) or other non-data information. The structure of a page may be other than the foregoing but essentially similar in the type of information included therein.
Single Level Cell (SLC) flash memory and Multi Level Cell (MLC) flash memory are two types of NAND flash memory. As the typical flash in the market, the erase block size of SLC flash is 128K+4K bytes and the erase block size of MLC flash is 256K+8K bytes. Thus, erase operations severe impact performance, particularly, when performed on large capacity memory. Another limitation of NAND flash memory has a finite numbers of times of erase cycles before it becomes unreliable. The number of erase operations that may be performed on NAND flash memory reliably is known to be limited to 10,000 to 1,000,000.
A comparison of MLC flash memory with SLC flash memory yields certain advantages and disadvantages by the former when used in consumer applications. The SLC flash memory, being memory cell-based, is capable of storing a single bit of data or information per cell whereas, MLC flash memory is capable of storing two bits of data per cell. Therefore, MLC flash memory has associate therewith twice the memory capacity of SLC flash memory assuming the same technology is used for manufacturing both. Moreover, the performance, reliability and durability costs of the MLC flash memory are higher. Thus, MLC flash memory being lower in cost and with greater memory capacity is desirably employed in consumer products. However, MLC flash memory is also known to have lower write speed than SLC flash memory thereby requiring a longer time to store information, such as digital pictures, therein. In a camera application, for example, this significantly impacts the photographers ability to take multiple shots fast.
A block of MLC flash memory includes M pages, M being an integer number with each page being N bytes, with N being an integer value. Fragment, as known in the computer industry, is created easily when the host sequentially sends less N bytes of data because MLC flash memory cannot be re-programmed, thus, the part of the N bytes that is not used to store data is wasted space leading to fragmentation or different parts of user files being located in different areas of memory.
Additionally, the life time of the MLC flash memory is limited to 10,000 erase cycles or operations. An entire block must be erased in MLC flash memory before a page can be re-programmed. Therefore, wear leveling techniques are needed to address the MLC flash re-programming problem.
Wear leveling is a technique used to distribute use of the memory cells within the MLC flash memory evenly thereby extending the lifetime of the latter. In wear leveling, a memory controller is used to re-map logical addresses, used to by a host to address memory, to different physical addresses, used to address the MLC flash memory, so that write operations are evenly distributed among the memory cells to extend the endurance of the MLC flash memory.
There is therefore a need for an MLC flash memory with higher performance by way of faster write operations thereto, less fragmentation and improved reliability.